One of post-processes for semiconductor manufacture is a process for testing a target object (e.g., a wafer) having a number of devices formed thereon by using a testing apparatus. The testing apparatus includes a loader chamber for transferring wafers accommodated in a cassette one by one; and a prober chamber for performing electrical characteristics tests of the wafers transferred from the loader chamber.
The loader chamber includes a wafer transfer mechanism that transfers the wafers one by one; and a pre-alignment mechanism (hereinafter referred to as a “sub chuck”) that arranges a direction of each wafer by referring to an orientation flat or a notch of the wafer while the wafer is being transferred by the wafer transfer mechanism. Meanwhile, the prober chamber includes a mounting table (hereinafter referred to as a “main chuck”) which moves in X, Y and Z directions and rotates forwardly or backwardly in θ direction while carrying the wafer thereon; a probe card disposed above the main chuck; and an alignment mechanism that aligns the wafer on the main chuck to probes of the probe card. Further, disposed at a head plate of the probe chamber is a test head which is brought into electrical contact with the probe card. A signal transfer is carried out between a tester and the probe card via the test head.
When a wafer test is performed, the wafer is carried out of the cassette by the wafer transfer mechanism and pre-aligned by the sub chuck in the loader chamber. After that, the wafer transfer mechanism mounts the wafer on the main chuck in the prober chamber. In the prober chamber, while the main chuck is moving in the X, Y, Z and θ directions, the alignment mechanism aligns the wafer to the probes of the probe card. Thereafter, the main chuck moves in the X and Y directions to position a first device on the wafer under the probes. Then, the main chuck moves up in the Z direction to thereby bring the device and the probes into electrical contact with each other, whereby performing a test of the first device. Upon the completion of the test of the first device, the main chuck moves down and performs an index feeding of the wafer so that the rest devices are tested subsequently. After the last device on the wafer is tested, the wafer is returned back to its original position inside the cassette via the main chuck and the wafer transfer mechanism, and, afterward, tests of rest wafers are performed subsequently.
During the test, static electricity is charged on the main chuck or the wafer due to an air friction generated when the main chuck moves or the like. This phenomenon is hard to avoid, and if not solved, there is a high likelihood that wiring structures of the devices might be damaged due to the influence of the static electricity during the test. In particular, with the recent trend of miniaturization of device structures, this problem is getting serious. Thus, Japanese Patent Laid-open Application No. 2003-218175 (Reference 1) proposes a charge eliminating mechanism for a main chuck. In this charge eliminating mechanism, the static electricity on the main chuck is eliminated while the wafer is being transferred between the wafer transfer mechanism and the main chuck.
With the charge eliminating mechanism in the Reference 1, however, the static electricity cannot be eliminated from the main chuck while the wafer test is being performed. That is, once a test of a single wafer is begun, the elimination of the static electricity cannot be performed until the test is finished. Accordingly, during the test of the single wafer, static electricity is gradually charged on the wafer and the main chuck. Therefore, with the progression of the test, there occurs a discrepancy in test results of devices, which results in deterioration of test reliability. In particular, with a recent device wiring structure made using a post-65-nm process, the influence of the static electricity becomes greater because a current applied during the test is very small. Thus, the influence of the static electricity upon the test result increases, resulting in deterioration of the test reliability, while causing a damage of the wiring structure in some extreme cases.